1. Field of the Invention
This invention relates to an integrated circuit package substrate, it especially relates to a pad design with a non-photo type mask of a high layout density integrated circuit package substrate.
2. Description of the Prior Art
Integrated circuits are typically housed within a plastic package commonly referred to as a quad flat pack (QFP). Flat packs contain a lead frame, which has a plurality of leads that are connected to an integrated circuit die. The die is encapsulated by a hard plastic housing, which mechanically supports and electrically insulates the integrated circuit. The leads are typically soldered to a printed circuit board.
Packaging techniques for integrated circuits have been developed in the past in an attempt to satisfy requirements for miniaturization in the integrated circuit industry. Improved methods for the miniaturization of integrated circuits enabling the integration of millions of transistor circuit elements into single integrated silicon embodied circuits, or chips, has resulted in an increased emphasis in methods to package these circuits with space efficiency.
Integrated circuits are created from a silicon wafer using various etching, doping, depositing and cutting steps that are well know in the art of fabricating integrated circuit devices. A silicon wafer may be comprised of a number of integrated circuit dies that each represents a single integrated circuit chip. Ultimately, the transfer molding plastic encasement around the chip with a variety of pin-out or mounting and interconnection schemes may package the chip. For example, M-Dip (Dual-In-Line-Plastic) provides a relatively flat, molded package having dual parallel rows of leads extending from the bottom for through-hole connection and mounting to an underlying printed circuit board. More compact integrated circuits allowing greater density on a printed circuit board are the SIP (Single-In-Line-Plastic), and SOJ (Small Outline J-leaded) molded case packages.
According to the amount of chips in the integrated circuit packages, the integrated circuit packages can be divided into a single chip package (SCP) type and a multi-chip package (MCP) type. The multi-chip package type also comprises a multi-chip module (MCM) type. For coupling an integrated circuit package and a circuit board, the integrated circuit package can be divided into a pin-through-hole (PTH) type and a surface mount technology (SMT) type. The pin-through-hole type has a plurality of acicular or sheet metal elements to be inserted into a socket or vias of the circuit board. The surface mount technology type element is adhered directly on the substrate and then is fixed by using a soldering process.
At present, the more advanced process for packaging an integrated circuit chip is a flip-chip package (FCP) process which can decrease the size of an integrated circuit package and to increase the circuit layout density of the integrated circuit package. The FCPprocess is to attach an integrated circuit chip on the package substrate directly at the active surface of the chip through a plurality of bumps to form an electric connection.
Referring to FIG. 1, this shows a diagram of a FCP structure in fixing a chip on a substrate with a photo-type solder mask. At first, a substrate 10 and a chip 40 is provided, wherein the substrate 10 comprises a plurality of conducting lines 25 of the layout circuits on the surface, a plurality of the bump pads 20, photo-type solder mask 30, and a pre-soldering 18 (can be omitted depending on the needs of products and processes). The chip 40 comprises a plurality of the die pads 45 and a plurality of solder bumps 15. The plural solder bumps 15 are connected to the chip 40 by the plural die pads 45. Then the plural solder bumps 15 are connected to the plural bump pads 20 or pre-soldering 18 respectively, which is on the substrate 10. The plural solder bumps 15 provide electric connection between the chip 40 and the substrate 10.
In the traditional integrated circuit package, the objective of using solder mask 30 is to avoid the conducting lines 25, from outside environmental damage, and to prevent a short circuit because of overflow of the solder bumps 15 in the following processes. Therefore, the solder mask 30 must cover the conducting lines 25 for protection. In order to provide better protective capabilities, an extra space is necessary for the photo-type solder mask alignment tolerance to avoid a short circuit problem. Therefore, the space between the bump pads 20 is limited for locating the conducting lines 25. In general, a solder mask define (SMD) mode is that the solder mask 30 covers all the conducting lines 25 and partially of each bump pad 20 and has openings smaller than each bump pad 20, as shown in FIG. 1; a non-solder mask define (NSMD) mode is that the solder mask 30 only covers the conducting lines 25 and has openings larger than each bump pad 20 (not shown in Figures). Even though the extra space is provided for the solder mask alignment tolerance, the traditional photo-type solder mask material still has problem of alignment inaccuracy, especially for a smaller package size or a higher layout circuit density. Furthermore, the photo-type solder mask has some reliability issues, such as the delamination with underfill, CTE mis-match, due to the photo-type solder mask material issues.
Due to the IC package substrate or circuit board needs the solder mask for protection in the traditional technology, the photo-type solder mask with the problem of photo alignment tolerance could not be avoided. Not only for the FCP with bump pads structure, the wire bonding package with bonding fingers or BGA package with ball pads could have the same problems. Therefore, the limited line routing space capability between bumps/bonding fingers, the reliability issues due to the photo-type solder mask material, and lower yield and higher cost for the solder mask process are disadvantages of the prior art.
In accordance with the background of the above-mentioned invention, the layout circuit density of the traditional integrated circuit package substrate with a photo-type solder mask cannot be successfully increased due to the photo-type solder mask alignment tolerance issue. The present invention provides a high-density integrated circuit package substrate and a method for the same to form a high layout circuit density IC substrate due to no further extra space required for solder mask, by using solder wettable metal as the material of the bump pad and forming a highly reliable non-photo type mask layer covering on the circuit lines.
The second objective of this invention is to provide a higher reliability IC package substrate due to a non-photo type mask in between.
The third objective of this invention is provided an IC package substrate with a higher process yield due to eliminating the solder mask photo process and a lower cost due to the shorter process, less material and less equipment investment.
In accordance with the foregoing objectives, the present invention provides a high layout density integrated circuit package substrate and a method for the same to avoid short circuit defects by using solder wettable metal as the material of the bump pads and forming a highly reliable mask layer to replace the conventional solder mask to cover the conductive lines. At first, a substrate is provided and a metal layer is formed on the substrate. Then the bump pads are defined by a first photo resist and formed on the metal layer, wherein the bump pads are made of solder wettable metal. Then the conductive lines are defined by a second photo resist, and the metal layer is etched to form a pattern of the bump pads and the conductive lines on the substrate. Next, a highly reliable non-photo type mask layer is formed to cover the substrate, the conductive lines, and the bump pads, and the part of the mask layer is removed to expose the bump pads. Finally, a mini bump or a pre-soldering can be formed on each of the bump pads as an interface between the bump on the chip and the bump pad on the substrate. Using the present invention can increase the circuit layout density on the substrate and the reliability of the integrated circuit package. Using the present invention can also increase the yield and the production efficiency of the integrated circuit package. Using the means and the method of the present invention can further decrease production costs of the integrated circuit package.